DEV_DECOUPLE_L1L2_EVT=Val_0x0, NAK_PER_ENH_HS=Val_0x0, DEV_L1_EXIT_BY_HW=Val_0x0, DEV_HS_NYET_BULK_SPR=Val_0x0, RESUME_OPMODE_HS_HOST=Val_0x0, FILTER_SE0_FSLS_EOP=Val_0x0, DEV_LSP_TAIL_LOCK_DIS=Val_0x0, DISUSB2REFCLKGTNG=Val_0x0, NAK_PER_ENH_FS=Val_0x0, TX_IPGAP_LINECHECK_DIS=Val_0x0, DEV_TRB_OUT_SPR_IND=Val_0x0
Global User Control Register 1
| LOA_FILTER_EN | LOA filter enable. If this bit is set, the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables. Note: This bit is valid only in Host mode. |
| OVRLD_L1_SUSP_COM | Overvload UTMI_L1_SUSPEND_COM. If this bit is set, the UTMI_L1_SUSPEND_COM_n is overloaded with the UTMI_SLEEP_n signal. This bit is usually set if the PHY stops the port clock during L1 sleep condition. |
| HC_PARCHK_DISABLE | Host parameter check disable. When this bit is set to 0x0 (by default), the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution, the xHC generates an event TRB with completion code indicating PARAMETER_ERROR. When the bit is set to 0x1, the xHC does not perform parameter checks and does not generate PARAMETER_ERROR completion code. |
| HC_ERRATA_ENABLE | Host Exit Latency Delta (ELD) enable. When this bit is set to 0x1, it enables the ELD support defined in the xHCI 1.0 Errata. This bit is used only in Host mode and should be set to 0x1. |
| L1_SUSP_THRLD_FOR_HOST | L1 suspend threshold in Host mode. This bit field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 0x1. For more details, refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit. |
| L1_SUSP_THRLD_EN_FOR_HOST | L1 suspend threshold enable in Host mode. This bit is used only in Host mode. The host controller asserts the UTMI_L1_SUSPEND_n and UTMI_SLEEP_n output signals as follows: The controller asserts the UTMI_L1_SUSPEND_n signal to put the PHY into deep low-power mode in L1 when both of the following are true: a) The HIRD/BESL value used is greater than or equal to the value in the L1_SUSP_THRLD_FOR_HOST bit. b) The L1_SUSP_THRLD_EN_FOR_HOST bit is set to 0x1. The controller asserts UTMI_SLEEP_n on L1 when one of the following is true: a) The HIRD/BESL value used is less than the value in the L1_SUSP_THRLD_FOR_HOST bit. b) This bit is set to 0x0. |
| DEV_HS_NYET_BULK_SPR | HS bulk OUT short packet gets NYET in Device mode This bit is applicable for Device mode only. If this bit is set, the device controller sends NYET response instead of ACK response for a successfully received bulk OUT short packet. If NYET is sent after receiving short packet, then the host would PING before sending the next OUT; this improves the performance as well as clears up the buffer/cache on the host side. Internal to the device controller, short packet (HCSPARAMS2[SPR] = 0x1) processing takes some time, and during this time, the USB is flow controlled. With NYET response instead of ACK on short packet, the host does not send another OUT-DATA without pinging in HS mode. This bit is quasi-static, that is, it must not be changed during device operation. 0 (Val_0x0): Default behavior, no change in device response. 1 (Val_0x1): Feature enabled, HS bulk OUT short packet gets NYET response. |
| RESUME_OPMODE_HS_HOST | Opmode in HS resume in Host mode This bit is used only in Host mode, and is for USB 2.0 opmode behavior in HS Resume. 0 (Val_0x0): When this bit is set to 0x0, the UTMI/ULPI opmode changes to normal 2 us after HS terminations change after EOR. This is the default behavior. 1 (Val_0x1): When this bit is set to 0x1, the UTMI opmode changes to normal along with HS terminations after EOR. |
| DISUSB2REFCLKGTNG | Disable REF_CLK gating for 2.0 PHY If REF_CLK gating is disabled, then the REF_CLK input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DSBLCLKGTNG] bit setting. 0 (Val_0x0): REF_CLK gating enabled for USB 2.0 PHY 1 (Val_0x1): REF_CLK gating disabled for USB 2.0 PHY |
| PARKMODE_DISABLE_FSLS | Disable park mode of FS/LS bus instances. This bit is used only in Host mode, and is for debug purpose only. When this bit is set to 0x1 all FS/LS bus instances in park mode disabled. |
| PARKMODE_DISABLE_HS | Disable park mode of HS bus instances. This bit is used only in Host mode. When this bit is set to 0x1, all HS bus instances park mode are disabled. To improve performance in park mode, the xHCI scheduler queues in three requests of 4 packets each for HS asynchronous endpoints in a micro-frame. But if a device is slow and if it NAKs more than 3 times, then it is rescheduled only in the next micro-frame. This could decrease the performance of a slow device even further. |
| NAK_PER_ENH_HS | Performance enhancement for HS in NAK. If a periodic endpoint is present, and if a bulk endpoint which is also active is being NAKed by the device, then this could result in decrease in performance of other HS bulk endpoint which is ACked by the device. Setting this bit to 0x1, enables the host controller to schedule more transactions to the async endpoints (bulk/control) and hence it improves the performance of the bulk endpoint. This control bit should be enabled only if the existing performance with the default setting is not sufficient for HS application. Setting this bit only controls, and is only required for HS transfers. 0 (Val_0x0): Enhancement not applied. 1 (Val_0x1): Enables performance enhancement for HS async endpoints in the presence of NAKs. |
| NAK_PER_ENH_FS | Performance enhancement for FS in NAK. If a periodic endpoint is present, and if a bulk endpoint which is also active is being NAKed by the device, then this could result in a decrease in performance of other Full-Speed bulk endpoint which is ACKed by the device. Setting this bit to 0x1, enables the HC to schedule more transactions to the async endpoints (bulk/control) and hence improves the performance of the bulk endpoint. This control bit should be enabled only if the existing performance with the default setting is not sufficient for Full-Speed application. Setting this bit will only control, and is only required for Full-Speed transfers. 0 (Val_0x0): Enhancement not applied. 1 (Val_0x1): Enables performance enhancement for FS async endpoints in the presence of NAKs. |
| DEV_LSP_TAIL_LOCK_DIS | Disable device LSP lock logic for tail TRB. 0 (Val_0x0): Default behavior, enables device LSP lock logic for tail TRB update. 1 (Val_0x1): Fix is disabled. |
| IP_GAP_ADD_ON | Inter packet gap add on. This bit field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. This should be programmed to a non-zero value only in case where it is need to increase the default inter packet delay calculations in the USB 2.0 MAC |
| DEV_L1_EXIT_BY_HW | Device in L1 hardware exit. When control transfers are in progress, the LPM is rejected (NYET response). Only after control transfers are completed (either with ACK/STALL), LPM is accepted. This bit is applicable for Device mode only. This field enables device controller sending remote wakeup for L1 if the device becomes ready for sending/accepting data when in L1 state. If the host expects the device to send remote wakeup signaling to resume after going into L1 in flow controlled state, then this bit can be set to send the remote wake signal automatically when the device controller becomes ready. This hardware remote wake feature is applicable only to bulk and interrupt transfers, and not for isochronous/control. For isochronous transfers, the host needs to do the wake-up and start the transfer. Device controller will not do remote-wakeup when isochronous endpoints get ready. The device software needs to keep the GUSB2PHYCFG0[ENBLSLPM] bit reset in order to keep the PHY clock to be running for keeping track of SOF intervals. 0 (Val_0x0): Default behavior, disables device L1 hardware exit logic. 1 (Val_0x1): Feature is enabled. |
| DEV_TRB_OUT_SPR_IND | OUT in TRB status short packet indication. This bit is applicable for Device mode only. If the device application (software/hardware) wants to know if a short packet was received for an OUT in the TRB status itself, then this feature can be enabled, so that a bit is set in the TRB writeback in the BUF_SIZE DWORD. The HCSPARAMS2[SPR] bit of the {trbstatus, RSVD, SPR, PCM1, bufsize} DWORD will be set during an OUT transfer TRB write back if this is the last TRB used for that transfer descriptor. This bit is quasi-static, that is, it must not be changed during device operation. 0 (Val_0x0): Default behavior, no change in TRB status DWORD 1 (Val_0x1): Feature enabled, OUT TRB status indicates Short Packet |
| TX_IPGAP_LINECHECK_DIS | Disable TX IPGAP LineState check. This bit is applicable for HS operation of MAC. If this feature is enabled, then the MAC operating in HS ignores the UTMI/ULPI LineState during the transmit of a token (during token-to-token and token-to-data IPGAP). When enabled, the controller implements a fixed 40-bit TXENDDELAY after the packet is given on UTMI and ignores the LineState during this time:
0 (Val_0x0): Default behavior, no change in LineState check. 1 (Val_0x1): Feature enabled, 2.0 MAC disables LineState check during HS transmit. |
| FILTER_SE0_FSLS_EOP | Filter SE0 detection in FS/LS or EOP. This bit is applicable for FS/LS operation. If this feature is enabled, then SE0 on the LineState is validated for two consecutive UTMI clock edges for EOP detection. This feature is applicable only in FS in Device mode and FS/LS mode of operation in Host mode.
0 (Val_0x0): Default behavior, no change in LineState check for SE0 detection in FS/LS. 1 (Val_0x1): Feature enabled, FS/LS SE0 is filtered for two clocks for detecting EOP. |
| DEV_DECOUPLE_L1L2_EVT | Device decoupled L1/L2 event. This bit is applicable for Device mode only. If this feature is enabled, L1 suspend and wake events have individual controls to enable/mask them. 0 (Val_0x0): Default behavior, no change in device events L1/L2 events are not decoupled. 1 (Val_0x1): Feature enabled, L1 and L2 events are separated. Separate event enable bits for L1 suspend and wake events. |